HIPAcc

Heterogeneous Image Processing Acceleration


About HIPAcc

HIPAcc is high-level programming framework for image processing applications developed at Hardware/Software Co-Design, Department of Computer Science at the University of Erlangen-Nuremberg, Germany. The framework is tailored for generating low-level CUDA, OpenCL, and Renderscript code optimized for target platform form a common description in a domain-specific language. Up to now, several publications on international conferences have been published that rely on the HIPAcc framework.

Hardware/Software Co-Design Friedrich Alexander University Erlangen-Nuremberg

It is considered as a matter of courtesy to link and mention HIPAcc if it is used in other projects.

Developers

Dr.-Ing. Richard Membarth
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Oliver Reiche, M.Sc.
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Website

Prof. Dr.-Ing. Michael Glaß
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Publications

Some selected publications that are based on HIPAcc as the underlying optimization framework:

R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Mastering Software Variant Explosion for GPU Accelerators.
In Proceedings of the 10th International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), pp. 123-132, Rhodes Island, Greece, August 27, 2012.

R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging.
In Proceedings of the 11th International Symposium on Parallel and Distributed Computing (ISPDC), pp. 211-218, Munich, Germany, June 25-29, 2012.

R. Membarth, F. Hannig, J. Teich, M. Körner and W. Eckert.
Generating Device-specific GPU Code for Local Operators in Medical Imaging.
In Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pp. 569-581, Shanghai, China, May 21-25, 2012.

R. Membarth, A. Lokhmotov and J. Teich.
Generating GPU Code from a High-level Representation for Image Processing Kernels.
In Proceedings of the 5th Workshop on Highly Parallel Processing on a Chip (HPPC), pp. 270-280, Bordeaux, France, Aug. 30, 2011.